Fast Blood Vessel Mapping by FPGA

Blood vessel mapping is a basic processing step in DR detection. In this study, our goal is to explore the parallel processing capability of modern FPGA chips, so that the computing costs for DR screening can be minimized. In the current study, we adopt the Xilinx Virtex 4 FX and LX based evaluation boards to design the communication and computing algorithms. The Virtex IV -FX series integrated with a PowerPC processor (PPC) makes it relative easy for the board to communicate with the network, but the FPGA has less logic fabirc for processing of the image. Virtex 4 - LX has more logic fabric but it has less dedicated hardware for communications and other supports.

Different image data transfer and processing pipelines need to be used for the two different types of architectures. For FX device, the input image is loaded from an external source to the PPC via one of the communication ports and is stored in the DDR SDRAM. Once the load is complete, image analysis begins and the PowerPC transfers and receives sub-blocks of the original image until completely processed. Because access to the DDR SDRAM is not shared between the PowerPC and the FPGA, the FPGA must temporarily store the sub-block being processed. In the LX device, the data is also loaded first, and then processing can directly start without waiting. The potential drawback, however, is lack of high level communication supports for LX devices. As of now, we have running codes on the devices, and refinements are udnerway to determine the optimal system configuration. A potential compromise is to use FX series as the communication processor and other LX devices for processing.