Configurable Computer Architectures

Most contemporary microprocessors, especially those used for embedded computing systems have an (RISC) architecture that supports a fixed set of instructions. It is practically impossible to change the instruction set of a deployed processor. An on-going collaborative study investigates the effectiveness of using partially configurable FPGA logic fabrics to enhance the subtle features (probing, logging, clocking, etc.) of the classical ASIC processor architecture at run time. A first generation prototype has been constructed using microprocessor evaluation boards interfaced to FPGAs. The FPGA is designed to be an interface between the microcontroller on the embedded processor board and the memory module. At the command of the microcontroller during run time, the FPGA is partially reconfigured from a memory management unit to a data cache. Despite the restriction of I/O and memory interface speeds, we were able to demonstrate the ability to provide adaptable functionality. A second generation prototype using Virtex IV is under study to investigate the cost-performance tradeoff in the reconfigurability of the data/instruction paths.

In general, it is a time consuming, tedious process to carry out the hardware-software co-development process of reconfigurable architectures. To cope with these practical yet critical issues, we have been using the Giano simulator to carry out experiments. Giano can be downloaded from MSDN MSDN download site. With the support of the simulator, codes written in high level language (HLL) (C, C++, etc.) for instruction set architecture (ISA) processors and the VHDL/Verilog codes written for FPGA can be compiled, simulated and interfaced to each other in different modes. It makes system level design, testing and debugging much easier and efficient than using the hardware prototypes directly. This is particularly important for optimization of reconfiguration options.